Comparators find application in a wealth of electronic circuits. When the input signals of the comparators are buried in noise, a comparator with hysteresis is needed as a rule. Comparators with hysteresis are achievable by external or internal positive feedback. Known from prior art is a CMOS comparator employing internal positive feedback as described, for example, in the text book “CMOS Analog Circuit Design” by Phillip E. Allen and Douglas R. Holberg, 2nd Edition, Oxford University Press 2002, pages 471 to 475.
The circuit diagram of the comparator with hysteresis as evident from this publication is illustrated in FIG. 1. This prior art comparator comprises a first NMOS-FET M10 whose gate is connected to the first input of the comparator, and a second NMOS-FET M20 whose gate is connected to the second input of the comparator. The sources of the two MOS-FETs are connected to a current source I. The drains of the two NMOS-FETs are connected via the main current paths of PMOS-FETs M30 and M40 to a supply voltage Vcc. The hysteresis is formed by the further PMOS-FETs M50 and M60. PMOS-FET M50 forms with PMOS-FET M30 a current mirror whilst PMOS-FET M60 forms with PMOS-FET M40 a further current mirror. The main current path of PMOS-FET M50 is connected to the main current path of the NMOS-FET M20 whilst the main current path of the PMOS-FET M60 is connected to the main current path of the NMOS-FET M10.
When e.g. the input voltage at input 1 is higher than the input voltage at input 2 a larger current is conducted via the source-drain circuit of the NMOS-FET M10 than via the source-drain circuit of the NMOS-FET M20. The majority of the current of the current source I then flows via Vcc, M30, M10 and current source I to ground whilst via M20 only a minor, or no, flow of current exists. In this arrangement the output signal at the output 70 of the comparator is HI. The gate voltage at the two current mirror transistors M40 and M60 is likewise HI.
As soon as the voltage at input 1, i.e. the gate of the NMOS-FET M10 becomes smaller than that at input 2, i.e. at the gate of NMOS-FET M20, the current flowing via supply voltage Vcc, M50, M20 and I gradually increases, causing the comparator to switch when the current flowing via M50 and M20 corresponds to the current flowing via M40 and M20. For this switching action to occur, the gate capacitance of the transistors M40 and M60, previously HI, needs to be discharged to ground voltage level which takes a certain time Dt. If the signals at the inputs of the comparator change in level with a high frequency, a relatively large current I is needed to ensure the continual fast recharging of the gate capacitances of the current mirror transistors M30, M50, M60 and M40. This is why the CMOS comparator known from prior art can only be put to use with high current consumption and at a high switching speed.